The present invention is generally related to static timing analysis of integrated circuit design and, more particularly, to a system and method for specifying a timing budget and window duration to be applied to a signal path under evaluation. The present invention is applicable to integrated circuits in which different, as well as identical, clock-type combinations might be utilized to clock circuitry operations.
Typical timing analysis tools are used in the analysis and design of integrated circuitry. These tools are useful in analyzing a signal path and determining whether or not, given a specified frequency of operation, the circuitry along that signal path is going to meet or exceed the timing requirements necessary for the proper circuitry operation at the specified frequency.
In the case where circuitry under analysis is provided a phase-type clock input signal, typical timing analysis tools are quite competent. However, where circuitry under analysis is being provided mixed clock-type signals, for example phase clock signals and pulse clock signals, these timing analysis tools are less reliable. More particularly, typical timing analysis tools are designed to analyze circuitry that is clocked via only phase-type clock signals. Thus, typical timing analysis tools are not equipped to competently handle circuitry that is clocked via pulse clock signals.
With typical static timing tools errors are often caused by clock signals which are not accurately interpreted. These xe2x80x9cambiguousxe2x80x9d clock signals occur frequently where the signal path under evaluation includes circuitry which is clocked by multiple clocks, and more particularly, where there is a mix of both phase-type clocks and pulse type clocks used to clock circuit operations. The signal path under analysis is generally a series of latches that include a driver latch and a receiver latch. A driver latch is a latch whose output feeds an input of a receiver latch.
FIG. 1 shows an example of a phase clock signal (CK) 20 and a pulse clock signal (PCK) 22. It can be seen that phase clock signal 20 and pulse clock signal 22 each have a leading edge 40 and a trailing edge 41. Typical timing analysis tools are designed for use in analyzing circuitry incorporating phase clock signals that are used to clock circuit operations. Phase clock type signals have a trailing edge 41 that follows a leading edge 40 after a period of time has elapsed. Phase clock signals typically have a duty-cycle of approximately 50%. Unlike phase-type clock signals a pulse-type clock signal has a very limited duty cycle and essentially provides for only a very limited duration of time between the leading edge 40 and the trailing edge 41. Since typical timing analysis tools are optimized for circuitry which is clocked via a phase-type clock signal, many inaccuracies occur when these tools are applied to analyze circuitry incorporating pulse-type clock signals. In the case of circuitry that is clocked via a pulse-type clock signal, the clock behavior is not as expected by typical static timing analysis tools. Thus, the typical static timing analysis tools fall short of reliable analysis of circuitry in which mixed type clock signals are provided to the circuitry under analysis.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
The present invention provides a system and method for static timing analysis of an integrated circuit. Briefly described, in architecture, the system can be implemented as follows. There is provided a sensor for determining whether the driver latch opens on an opening edge or a trailing edge of a reference clock, as well as a sensor for determining whether the receiver latch opens on a opening edge or a closing edge of the reference clock. Further a sensor for determining whether the receiver latch closes on an opening edge or a closing edge of the reference clock is provided, as is a sensor for determining the relation between the reference clock edge on which the receiving latch opens and the reference clock edge on which the receiving latch closes. A controller determines a timing budget based upon the determination (input) from each of the sensors.
The present invention can also be viewed as providing a method for static timing analysis of an integrated circuit. In this regard, the method can be broadly summarized by the following steps: identifying a signal path composed of a driver latch; logic gating and a receiver latch for evaluation; defining a reference clock having an opening edge and closing edge; determining whether the driver latch opens on an opening edge or a trailing edge of the reference clock; determining whether the receiver latch opens on an opening edge or a closing edge of the reference clock; determining whether the receiver latch closes on an opening edge or a closing edge of the reference clock; determining the relation between the reference clock edge on which the receiving latch opens and the reference clock edge on which the receiving latch closes; and assigning a timing budget based upon the above determinations.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.